Referring to FIG. 1, a conventional phase-lock loop (PLL) circuit 10 used for performing clock and data recovery in a serial data communication device is shown. A voltage controlled oscillator (VCO) 12 generates a full-rate clock which is divided by "N" (an integer) by a divider (FBDIV) 14. The divided clock is fed to a phase-frequency detector (PFD) 16. The PFD 16 receives a reference clock signal REFCLK.sub.-- IN which is typically divided by N version of the data rate. The PFD 16 compares the two clocks and generates pump-up and pump-down signals which are then fed to a charge-pump/filter 18 through a multiplexer 20 that is controlled by a signal LLC. The signal LLC controls the "locking" of the PLL 10 to the signal REFCLK.sub.-- IN or to the signal DATA. When the PLL 10 is frequency locked to the signal REFCLK, the multiplexer 20 is switched to select the signal DATA, through a phase detector (PD) 22 for the closed loop by using the signal LLC. The phase detector 22 then locks to the signal DATA and generates a signal re-timed DATA and recovered a signal CLOCK. This implementation requires the use of a full-rate phase detector 22 and a full-rate VCO 12. The VCO 12 generates a single phase of the clock. The divider 14 is also full-rate single-phase divider.
The circuit 10 may require full-rate components for the phase detector 22 and the VCO 12. Additionally, the phase detector 22 may have to be implemented as a linear full-rate phase detector. The full-rate operation may require higher power components.